? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice 1 cat24c01b k-bit serial eeprom doc. no. 1081, rev. e pin configuration block diagram pin functions pin name function nc no connect sda serial data/address scl serial clock v cc +1.8v to +6.0v power supply v ss ground test test input (gnd, v cc or floating) dip package (p, l, gl) soic package (j, w, gw) features 2-wire serial interface 1.8 to 6.0volt operation low power cmos technology 4-byte page write buffer self-timed write cycle with auto-clear 1,000,000 program/erase cycles 100 year data retention 8-pin dip, 8-pin soic, 8 pin tssop or 8-pin msop commercial, industrial and automotive temperature ranges "green" package options available description the cat24c01b is a 1k-bit serial cmos eeprom internally organized as 128 words of 8 bits each. catalysts advanced cmos technology substantially reduces de- vice power requirements. the cat24c01b features a 4-byte page write buffer. the device operates via a 2- wire serial interface and is available in 8-pin dip, 8-pin soic, 8-pin tssop or 8-pin msop. tssop package (u, y, gy) d out ack sense amps shift registers control logic word address buffers start/stop logic state counters e 2 prom v cc external load column decoders xdec data in storage high voltage/ timing control v ss scl sda nc nc nc v ss 1 2 3 4 8 7 6 5 v cc test scl sda v cc scl sda 1 2 3 4 8 7 6 5 v ss nc nc nc test v cc scl sda 1 2 3 4 8 7 6 5 v ss nc nc nc test msop package (r, z, gz) 8 7 6 5 v cc test scl sda nc nc nc v ss 1 2 3 4 eeprom
cat24c01b 2 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice absolute maximum ratings* temperature under bias ................. C 55 c to +125 c storage temperature ....................... C 65 c to +150 c voltage on any pin with respect to ground (1) ........... C 2.0v to +v cc + 2.0v v cc with respect to ground ............... C 2.0v to +7.0v package power dissipation capability (ta = 25 c) .................................. 1.0w lead soldering temperature (10 secs) ............ 300 c output short circuit current (2) ........................ 100ma *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device performance and reliability. reliability characteristics symbol parameter min max units reference test method n end (3) endurance 1,000,000 cycles/byte mil-std-883, test method 1033 t dr (3) data retention 100 years mil-std-883, test method 1008 v zap (3) esd susceptibility 2000 volts mil-std-883, test method 3015 i lth (3)(4) latch-up 100 ma jedec standard 17 d.c. operating characteristics v cc = +1.8v to +6.0v, unless otherwise specified. limits symbol parameter min typ max units test conditions i cc power supply current 3 ma f scl = 100 khz i sb (5) standby current (v cc = 5.0v) 1 av in = gnd or v cc i li input leakage current 10 av in = gnd to v cc i lo output leakage current 10 av out = gnd to v cc v il input low voltage C 1v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol1 output low voltage (v cc = 3.0v) 0.4 v i ol = 3 ma v ol2 output low voltage (v cc = 1.8v) 0.5 v i ol = 1.5 ma note: (1) the minimum dc input voltage is C 0.5v. during transitions, inputs may undershoot to C 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc + 2.0v for periods of less than 20ns. (2) output shorted for no more than one second. no more than one output shorted at a time. (3) these parameter are tested initially and after a design or process change that affects the parameter according to appropriat e aec-q100 and jedec test methods. (4) latch-up protection is provided for stresses up to 100 ma on address and data pins from C 1v to v cc +1v. (5) maximum standby current (i sb ) = 10 a for the automotive and extended automotive temperature range. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test max units conditions c i/o (3) input/output capacitance (sda) 8 pf v i/o = 0v c in (3) input capacitance (a0, a1, a2, scl, wp) 6 pf v in = 0v
cat24c01b 3 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice a.c. characteristics v cc = +1.8v to +6.0v, c l =1ttl gate and 100pf (unless otherwise specified). read & write cycle limits symbol parameter 1.8v, 2.5v 4.5v-5.5v min max min max units f scl clock frequency 100 400 khz t i (1) noise suppression time 100 100 ns constant at scl, sda inputs t aa scl low to sda data out 3.5 1 s and ack out t buf (1) time the bus must be free before 4.7 1.2 s a new transmission can start t hd:sta start condition hold time 4 0.6 s t low clock low period 4.7 1.2 s t high clock high period 4 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 100 ns t r (1) sda and scl rise time 1 0.3 s t f (1) sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 100 100 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. the write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. during the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its input. write cycle limits symbol parameter min typ max units t wr write cycle time 10 ms power-up timing (1)(2) symbol parameter max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms
cat24c01b 4 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice functional description the cat24c01b uses a 2-wire data transmission pro- tocol. the protocol defines any device that sends data to the bus to be a transmitter and any device receiving data to be a receiver. data transfer is controlled by the master device which generates the serial clock and all start and stop conditions for bus access. the cat24c01b operates as a slave device. both the master and slave devices can operate as either transmitter or receiver, but the master device controls which mode is activated. pin descriptions scl: serial clock the cat24c01b serial clock input pin is used to clock all data transfers into or out of the device. this is an input pin. sda: serial data/address the cat24c01b bidirectional serial data/address pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wired with other open drain or open collector outputs. 2-wire bus protocol the following defines the features of the 2-wire bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock line is high will be interpreted as a start or stop condition. figure 2. write cycle timing figure 1. bus timing figure 3. start/stop timing 5020 fhd f05 5020 fhd f04 5020 fhd f03 t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh t wr stop condition start condition address ack 8th bit byte n scl sda start bit sda stop bit scl
cat24c01b 5 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat24c01b monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledg- ing device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat24c01b responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8- bit byte. when the cat24c01b is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowl- edge, the cat24c01b will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. write operations byte write in the byte write mode, the master device sends the start condition and the slave address information (with the r/ w bit set to zero) to the slave device. after the slave generates an acknowledge, the master sends the byte address that is to be written into the address pointer of the cat24c01b. after receiving another acknowl- edge from the slave, the master device transmits the data byte to be written into the addressed memory location. the cat24c01b acknowledge once more and the master generates the stop condition, at which time the device begins its internal programming cycle to nonvolatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. page write the cat24c01b writes up to 4 bytes of data in a single write cycle, using the page write operation. the page write operation is initiated in the same manner as the byte write operation, however instead of terminating after the initial word is transmitted, the master is allowed to send up to 3 additional bytes. after each byte has been transmitted the cat24c01b will respond with an ac- knowledge, and internally increment the low order ad- dress bits by one. the high order bits remain un- changed. if the master transmits more than 4 bytes prior to sending the stop condition, the address counter wraps around, and previously transmitted data will be overwritten. once all 4 bytes are received and the stop condition has been sent by the master, the internal programming cycle begins. at this point all received data is written to the cat24c01b in a single write cycle. note: catalyst semiconductor does program all "1" data into the entire memory array prior to shipping our eeprom products. figure 4. acknowledge timing 5020 fhd f06 acknowledge 1 start scl from master 89 data output from transmitter data output from receiver
cat24c01b 6 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 6. page write timing figure5. byte write timing ing with an acknowledge and by issuing a stop condition. refer to figure 7 for the start word address, read bit, acknowledge and data transfer sequence. sequential read the sequential read operation can be initiated after the 24c01b sends the initial 8-bit byte requested, the master will respond with an acknowledge which tells the device it requires more data. the cat24c01b will continue to output an 8-bit byte for each acknowledge sent by the master. the operation is terminated when the master fails to respond with an acknowledge, thus sending the stop condition. the data being transmitted from the cat24c01b is output sequentially with data from address n followed by data from address n+1. the read operation address counter increments all of the cat24c01b address bits so that the entire memory array can be read during one operation. if more than bytes are read out, the counter will wrap around and continue to clock out data bytes. acknowledge polling the disabling of the inputs can be used to take advan- tage of the typical write cycle time. once the stop condition is issued to indicate the end of the host s write operation, the cat24c01b initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the byte address for a write operation. if the cat24c01b is still busy with the write operation, no ack will be returned. if the cat24c01b has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. read operations the read operation for the cat24c01b is initiated in the same manner as the write operation with the one exception that the r/ w bit is set to a one. two different read operations are possible: byte read and se- quential read. it should be noted that the ninth clock cycle of the read operation is not a "don't care." to terminate a read operation, the master must either issure a stop condition during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. byte read to initiate a read operation, the master sends a start condition followed by a seven bit word address and a read bit. the cat24c01b responds with an acknowl- edge and then transmits the eight bits of data. the read operation is terminated by the master; by not respond- bus activity: sda line data n+3 a c k a c k data n s t o p s a c k data n+1 a c k s t a r t p word address(n) m s b l s b r / w bus activity: bus activity: sda line a c k a c k data n s t o p s s t a r t p word address(n) m s b l s b r / w bus activity:
cat24c01b 7 doc. no. 1081, rev. e ? 2005 by catalyst semiconductor, inc. characteristics subject to change without notice figure 7. byte read timing bus activity master sda line data n+x a c k a c k data n+1 s t o p a c k data n+2 a c k p address r / w data n bus activity cat24c01b figure 8. sequential read timing ordering information notes: (1) the device used in the above example is a 24c01bji-1.8te13 (soic, industrial temperature, 1.8 volt to 6 volt operating voltage, tape & reel) (2) product die revision letter is marked on top of the package as a suffix to the production date code (e.g. aywwa). for additi onal information, please contact your catalyst sales office. bus activity master sda line a c k a c k data n s t o p s s t a r t p word address(n) m s b l s b r / w bus activity cat24c01b prefix device # suffix 24c01b j i te13 product number 24c01b: 1k tape & reel package p: pdip j: soic, jedec u: tssop r: msop l: pdip (lead-free, halogen-free) w: soic (lead-free, halogen-free) y: tssop (lead-free, halogen-free) z: msop (lead-free, halogen-free) gl: pdip (lead-free, halogen-free, nipdau lead plating) gw: soic (lead-free, halogen-free, nipdau lead plating) gy: tssop (lead-free, halogen-free, nipdau lead plating) gz: msop (lead-free, halogen-free, nipdau lead plating) operating voltage blank: 2.5v - 6.0v 1.8: 1.8v - 6.0v -1.8 cat temperature range blank = commercial (0 c to 70 c) i = industrial (-40 c to 85 ? c) a = automotive (-40 c to 105 c) e = extended (-40 c to 125 c) optional company id rev a (2) die revision
catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.caalyst-semiconductor.com copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp ae 2 minipot catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the company s corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. publication #: 1081 revison: e issue date: 08/03/05 revision history e t a dn o i s i v e rs t n e m m o c 4 0 0 2 / 7 1 / 4 0b n o i t a m r o f n i g n i r e d r o e t a d p u r e b m u n . v e r e t a d p u 4 0 0 2 / 7 / 7c n o i t a m r o f n i g n i r e d r o o t n o i s i v e r e i d d e d d a 5 0 / 3 0 / 8 0e n o i t a m r o f n i g n i r e d r o e t a d p u
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